In fabrication of semiconductor devices, BEoL VNCAPs frequently offer higher capacitance density and lower cost over other technologies such as metal-insulator-metal (MIM) planar capacitors. Initially, traditional BEoL VNCAP designs utilized litho-etch (LE) processes for a 45 to 90 nanometer (nm) technology node. Next, traditional BEoL VNCAP designs utilized litho-etch-litho-etch (LELE) processes for a 45-28 nm technology node. However, to allow for even smaller technology nodes, traditional litho-etch-litho-etch-litho-etch (LELELE) processes may increase cost and manufacturing risk while reducing a yield of resulting devices, particularly for a 10 nm technology node and beyond.
A need therefore exists for a methodology enabling incorporation of BEoL VNCAPs in ICs, particularly, for the 10 nm technology node and beyond, and a resulting device.